Verigen Docs (w.i.p.)
Welcome to VERIGEN!
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Verigen is an open-source software that integrates functions including Verilog code simulation, synthesis, netlist output, and layout and routing. This software is released under the MIT License.
Installation and Configuration
Prerequisites:
- Linux (Fedora 41 best, or any Unix-like OS)
- Verigen tools, include
iverilog
yosys
netlistsvg
vvp
- In fact, these are not necessary. If you don’t, you can simply run it in the Verigen shell environment. Verigen has offered you these tools.
Steps to Install:
Clone the repository:
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2git clone https://github.com/albertc9/Verigen.git
cd VerigenBuild and configure:
Make sure your environment is properly set up to run Verigen.
Inside theverigen
directory, run:1
2chmod +x build
./buildAfter installation, you should be able to run
verigen
directly from anywhere in the terminal.
Simple Instructions
Running Verigen:
Enter the interactive Verigen shell:
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verigen
This will enter the Verigen interactive shell. From here, you can enter Verigen commands directly. You can also type commands directly into the terminal.
Run Verilog simulation:
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verigen testbench.v dut.v
This will run a simulation. If you add codes like
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2
3
4initial begin
$dumpfile("testbench.vcd");
$dumpvars(0, testbench);
endto your testbench code, you’ll additionally get a
.vcd
file.Generate netlist and SVG:
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verigen -a dut.v
This command generates a JSON netlist and an SVG diagram for the given Verilog file.
Generate only netlist (no SVG):
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verigen -j dut.v
This command generates only the JSON netlist without the SVG diagram.
Generate only SVG (no netlist):
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verigen -s dut.v
This command generates only the SVG diagram without the netlist.
Check Verigen version:
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verigen --version
Displays the current version of Verigen. And can also verify installation and configuration.
Get help:
Inside the interactive shell, type:1
.help
This will show you a list of all available commands and options in Verigen.
License
This software is released under the MIT License.
For more information, please refer to the document:
- Title: Verigen Docs (w.i.p.)
- Author: Albert Cheung
- Created at : 2025-02-18 21:42:59
- Updated at : 2025-02-20 19:51:19
- Link: https://www.albertc9.github.io/2025/02/18/verigen-docs/
- License: This work is licensed under CC BY-NC-SA 4.0.